1. Field of the Invention
The present invention relates to a data processing system, particularly to a data processing system which provides a plurality of vector registers comprising a plurality of elements between a main memory unit and an operational unit, transfers desired data to said vector registers from the main memory unit and holds it therein, and carries out various processings such as logical operations by sequentially accessing the elements in said vector registers.
2. Description of the Prior Art
In a data processing system where data of a main memory unit is usually buffered to a plurality of vector registers consisting of plurality of elements and where operations such as logical operation are carried out by extracting the data from said vector register, the vector registers are arranged in units of a bank where a plurality of banks are used and arithmethic operations are performed by sequentially addressing a continuous data element in the same bank unit.
As a typical example of the data processing system employing such a system, the CRAY-1 Computer System described in the magazine "Communications of the ACM" Volume 21, Number 1, 1978, PP63-72 is generally known. However, according to the existing system, when the bank storing the data, which is considered the object of operation, is once started to be used for a vector operation etc., such bank becomes busy for a long period. The bank remains busy until the operations for the series of a plurality of data elements of the vector operation is finished, and as a result, the elements in the other addresses in the same bank can no longer be used.
On the page 66 of the ACM article previously mentioned, a structure where a total of eight vector registers from V0 to V7 are arranged is disclosed.
In this existing system, for example, when an instruction, "add the contents of vector registers V0 and V1 and store an result to the vector register V2" and the instruction, "multiply the data obtained as a result of addition being stored in the vector register V2 and the content of vector register V3 and then store the result to the vector register V4" are issued, after the data element obtained as the result of first addition is stored in the vector register V2, the contents of the pertinent vector register V2 is sequentially considered as the object of operation for the succeeding multiplication instructions. However, since the vector register V2 continuously stores the data obtained as the result of addition, it does not become idle until the data indicating the result of the final addition is stored. Therefore, even when the data considered as the object of operation exists within the vector register V2, the succeeding multiplication instructions cannot use it, except for only one case where the succeeding multiplication instructions are issued with a timing such that the data obtained as the result of the first addition by the preceding addition instruction is output from an adder circuit. In such a case, the succeeding multiplication instructions can be executed in parallel with the execution of the addition instruction by extracting the data to be stored in to the vector register V2 from the adder circuit through a bypass route. But, this case is an exceptional operation where the succeeding instruction happens to be issued at the one limited timing. Usually, instructions are issued at a random timing and the succeeding instructions are, in general, queued until the operations for a preceding instruction for the same bank terminates.
The above-discussed system brings about a result such that not only the average instruction execution time of a vector instruction becomes long but also the effective degree of use of the vector registers can be reduced drastically, and in addition the amount of data that can be accommodated in the vector register is also reduced.